MICRO-32 Final Program

Monday, Nov. 15^th

08:00-18:00 Workshops & Tutorials Day

• The 2nd Workshop on Feedback-Directed Optimization (FDO)    (full program)
  Chairs: Brad Calder, UCSD; Chris Newburn, Intel
  
• The 1st Workshop on Media Processors and DSPs (MP-DSP)
  Chairs: Freddy Gabbay, Mellanox; Corinna Lee, ATI
  
• Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design    (slides-PDF)
  Chairs: Srilatha Manne, Compaq; Trevor Mudge, Michigan; Dirk Grunwald, Colorado

Tuesday, Nov. 16^th

08:30-10:00 Welcome & Key Note
             Chair: Ronny Ronen, Intel Israel

• Key note: Fred Pollack  Intel Corporation, Microprocessor Research Labs
  New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies    (slides-PS)

10:30-12:30 Faster FrontEnd
              Chair: Gary Tyson, The University of Michigan, Ann Arbor

• Control Independence in Trace Processors    (slides-PS)
  Eric Rotenberg (North Carolina State University), James E Smith (University of Wisconsin, Madison)
• Fetch Directed Instruction Prefetching    (slides-PPT)
  Glenn Reinman, Brad Calder (University of California, San Diego), Todd Austin (University of Michigan)
• Improving Branch Predictors by Correlating on Data Values    (slides-PS/PPT)
  Timothy Heil, Zak Smith, James E Smith (University of Wisconsin, Madison)
• Instruction Fetch Mechanisms for Multipath Execution Processors   (slides-PDF)
  Artur Klauser, Dirk Grunwald (University of Colorado, Boulder)

13:30-15:00 3D & MultiMedia
              Chair: Matthew Farrens, University of California, Davis

• A Superscalar 3D Graphics Engine    (slides-PPT)
  Andrew Wolfe, Derek B Noonburg (S3 Incorporated)
• Dynamic 3D Graphics Workload Characteriza-tion and the Architectural Implications    (slides-PS)
  Tulika Mitra, Tzi-cker Chiueh (SUNY at Stony Brook)
• Exploiting a New Level of DLP in Multimedia Applications ^(s)    (slides-PPT)
  Jesus Corbal, Mateo Valero (Universitat Politecnica de Catalunya, Barcelona), Roger Espasa (Compaq Computer Corporation)

15:30-17:00 Efficient Embedded Processors
              Chair: Kemal Ebcioglu, IBM

• Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors    (slides-PDF)
  Sergei Y Larin, Thomas M Conte (North Carolina State University)
• Evaluation of a High Performance Code Compression Method    (slides-PDF)
  Charles R Lefurgy, Eva M Piccininni, Trevor N Mudge (University of Michigan)
• Low-Cost Branch Folding for Embedded Applications with Small Tight Loops ^(s)    (slides-PS)
  Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends (M*CORE Technology Center)

18:00 - Welcone Reception

20:00 - ACM SIGMICRO / IEEE TC-MARCH Business Meeting

Wednesday, Nov. 17^th

08:30-10:30 Memory Hierarchy
              Chair: Doug Burger, University of Texas, Austin

• Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems    (slides-PPT)
  Santosh G Abraham, Scott A Mahlke (Hewlett-Packard Laboratories, Palo Alto)
• Hardware Identification of Cache Conflict Misses    (slides-PPT)
  Jamison D Collins, Dean M Tullsen (University of California, San Diego)
• Access Region Locality for High-Bandwidth Processor Memory System Design    (slides-PPT)
  Sangyeun Cho (Samsung Electronics Co.), Pen-Chung Yew (University of Minnesota), Gyungho Lee (Iowa State University)
• Code Transformations to Improve Memory Parallelism (s)    (slides-PS)
  Vijay S Pai, Sarita Adve (Rice University)

11:00-12:30 Better Scheduling
              Chair: Stephan Jourdan, Intel

• Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results    (slides-PS)
  Daniel A Connors, Wen-mei W Hwu (University of Illinois)
• Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing ^(s)     (slides-PPT)
  Soner Onder (Michigan Technological University), Rajiv Gupta (University of Arizona)
• Read-After-Read Memory Dependence Prediction ^(s)    (slides-PDF)
  Andreas Moshovos (Northwestern University), Gurindar S Sohi (University of Wisconsin, Madison)
• Delaying Physical Register Allocation Through Virtual-Physical Registers ^(s)    (slides-PS)
  Teresa Monreal, Victor Vinals (Universidad de Zaragoza), Antonio Gonzalez, Mateo Valero, Jose Gonzalez (Universitat Politecnica de Catalunya, Barcelona)

20:00 - Dinner at the National Science Museum

Thursday, Nov. 18^th

08:30-10:00 Key Note
              Chair: Gabby Silberman, IBM, Canada

• Key note: Dr. Bruce D. Shriver, Genesis 2, Inc.
  Core Technologies in Hardware and Software    (slides-PDF)

10:30-12:30 Novel Microarchitectures and Multithreading
              Chair: Brad Calder, University of California, San Diego

• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design   (slides-PDF)
  Todd M Austin (University of Michigan)
• Exploiting ILP in Page-Based Intelligent Memory
  Mark H Oskin, Justin Hensley, Diana Keen, Frederic T Chong, Matthew Farrens, Aneet Chopra (U. of California, Davis)
• The Use of Multithreading for Exception Handling    (slides-PDF)
  Craig B Zilles, Gurindar S Sohi (University of Wisconsin, Madison), Joel S Emer (Compaq Computer Corporation)
• Value Prediction for Speculative Multithreaded Architectures ^(s)    (slides-PPT)
  Pedro Marcuello, Jordi Tubella, Antonio Gonzalez (Universitat Politecnica de Catalunya, Barcelona)

13:30-14:30 Low Power Enhancements
              Chair: Mateo Valero, Universitat Politecnica de Catalunya, Spain

• Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors    (slides-PS)
  Enric Musoll (XStream Logic, Inc.)
• Selective Cache Ways: On-Demand Cache Resource Allocation
  David H Albonesi (University of Rochester)

15:00-16:30 Compilers
              Chair: David Bernstein, IBM, Israel

• Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs    (slides-PPT)
  Jay Bharadwaj, Kishore N Menezes (Intel Corporation), Chris McKinsey (Star*Core Technology Center)
• Balance Scheduling: Weighting Branch Tradeoffs in Superblocks    (slides-PPT)
  Alexandre Eichenberger (North Carolina State University), Waleed Meleis (Northeastern University)
• Optimizations and Oracle Parallelism with Dynamic Translation    (slides-PDF)
  Kemal Ebcioglu, Erik R Altman, Sumedh Sathaye, Michael Gschwind (IBM T.J. Watson Research Center)

16:30-17:00 Summary

(s) indicates Short Paper

Micro-32 Home Page

Last updated: November 11, 1999