MICRO-32 Final Program THE 32nd ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE with special emphasis on Instruction-Level Parallel Processing Haifa, Israel, November 15-18, 1999 Sponsored by IEEE TC-MARCH and ACM SIGMICRO ================================================================= MICRO-32 general information, and registration & accommodation forms are now available at the MICRO-32 web-site: http://huron.cs.ucdavis.edu/Micro32 ================================================================= The annual MICRO conference has provided a key venue for the dissemination of ideas and advances in the field of computer microarchitecture research. MICRO is the premier forum for discussing and debating issues relating to instruction-level parallelism, compilation techniques and micro-architectures. ================================================================= Monday, Nov. 15th 08:00-18:00 Workshops & Tutorials Day * The 2nd Workshop on Feedback-Directed Optimization (FDO) Chairs: Brad Calder, UCSD; Chris Newburn, Intel * The 1st Workshop on Media Processors and DSPs (MP-DSP) Chairs: Freddy Gabbay, Mellanox; Corinna Lee, ATI * Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design Chairs: Srilatha Manne, Compaq; Trevor Mudge, Michigan; Dirk Grunwald, Colorado ================================================================= Tuesday, Nov. 16th 08:30-10:00 Welcome & Key Note Chair: Ronny Ronen, Intel Israel * Key note: Fred Pollack Intel Corporation, Microprocessor Research Labs New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies 10:30-12:30 Faster FrontEnd Chair: Gary Tyson, The University of Michigan, Ann Arbor * Control Independence in Trace Processors Eric Rotenberg (North Carolina State University), James E Smith (University of Wisconsin, Madison) * Fetch Directed Instruction Prefetching Glenn Reinman, Brad Calder (University of California, San Diego), Todd Austin (University of Michigan) * Improving Branch Predictors by Correlating on Data Values Timothy Heil, Zak Smith, James E Smith (University of Wisconsin, Madison) * Instruction Fetch Mechanisms for Multipath Execution Processors Artur Klauser, Dirk Grunwald (University of Colorado, Boulder) 13:30-15:00 3D & MultiMedia Chair: Matthew Farrens, University of California, Davis * A Superscalar 3D Graphics Engine Andrew Wolfe, Derek B Noonburg (S3 incorporated) * Dynamic 3D Graphics Workload Characteriza-tion and the Architectural Implications Tulika Mitra, Tzi-cker Chiueh (SUNY at Stony Brook) + Exploiting a New Level of DLP in Multimedia Applications Jesus Corbal, Mateo Valero (Universitat Politecnica de Catalunya, Barcelona), Roger Espasa (Compaq Computer Corporation) 15:30-17:00 Efficient Embedded Processors Chair: Kemal Ebcioglu, IBM * Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors Sergei Y Larin, Thomas M Conte (North Carolina State University) * Evaluation of a High Performance Code Compression Method Charles R Lefurgy, Eva M Piccininni, Trevor N Mudge (University of Michigan) + Low-Cost Branch Folding for Embedded Applications with Small Tight Loops Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends (M*CORE Technology Center) 18:00 - Welcome Reception. 20:00 - ACM SIGMICRO / IEEE TC-MARCH Business Meeting ================================================================= Wednesday, Nov. 17th 08:30-10:30 Memory Hierarchy Chair: Doug Burger, University of Texas, Austin * Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems Santosh G Abraham, Scott A Mahlke (Hewlett-Packard Laboratories, Palo Alto) * Hardware Identification of Cache Conflict Misses Jamison D Collins, Dean M Tullsen (University of California, San Diego) * Access Region Locality for High-Bandwidth Processor Memory System Design Sangyeun Cho (Samsung Electronics Co.), Pen-Chung Yew (University of Minnesota), Gyungho Lee (Iowa State University) + Code Transformations to Improve Memory Parallelism Vijay S Pai, Sarita Adve (Rice University) 11:00-12:30 Better Scheduling Chair: Stephan Jourdan, Intel * Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results Daniel A Connors, Wen-mei W Hwu (University of Illinois) + Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing Soner Onder (Michigan Technological University), Rajiv Gupta (University of Arizona) + Read-After-Read Memory Dependence Prediction Andreas Moshovos (Northwestern University), Gurindar S Sohi (University of Wisconsin, Madison) + Delaying Physical Register Allocation Through Virtual-Physical Registers Teresa Monreal, Victor Vinals (Universidad de Zaragoza), Antonio Gonzalez, Mateo Valero, Jose Gonzalez (Universitat Politecnica de Catalunya, Barcelona) 13:30 - Excursion. The old city of Acre 20:00 - Dinner at the National Science Museum ================================================================= Thursday, Nov. 18th 08:30-10:00 Key Note Chair: Gabby Silberman, IBM, Canada * Key note speech by Dr. Bruce D. Shriver, Genesis 2, Inc. Core Technologies in Hardware and Software 10:30-12:30 Novel Microarchitectures and Multithreading Chair: Brad Calder, University of California, San Diego * DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design Todd M Austin (University of Michigan) * Exploiting ILP in Page-Based Intelligent Memory Mark H Oskin, Justin Hensley, Diana Keen, Frederic T Chong, Matthew Farrens, Aneet Chopra (U. of California, Davis) * The Use of Multithreading for Exception Handling Craig B Zilles, Gurindar S Sohi (University of Wisconsin, Madison), Joel S Emer (Compaq Computer Corporation) + Value Prediction for Speculative Multithreaded Architectures Pedro Marcuello, Jordi Tubella, Antonio Gonzalez (Universitat Politecnica de Catalunya, Barcelona) 13:30-14:30 Low Power Enhancements Chair: Mateo Valero, Universitat Politecnica de Catalunya, Spain * Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors Enric Musoll (XStream Logic, Inc.) * Selective Cache Ways: On-Demand Cache Resource Allocation David H Albonesi (University of Rochester) 15:00-16:30 Compilers Chair: David Bernstein, IBM, Israel * Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs Jay Bharadwaj, Kishore N Menezes (Intel Corporation), Chris McKinsey (Star*Core Technology Center) * Balance Scheduling: Weighting Branch Tradeoffs in Superblocks Alexandre Eichenberger (North Carolina State University), Waleed Meleis (Northeastern University) * Optimizations and Oracle Parallelism with Dynamic Translation Kemal Ebcioglu, Erik R Altman, Sumedh Sathaye, Michael Gschwind (IBM T.J. Watson Research Center) 16:30-17:00 Summary + indicates short paper ================================================================= Conference Chairs General: Ronny Ronen, Intel Israel Matthew Farrens, UC Davis Program: Ilan Spillinger, Intel Israel Finance: David Bernstein, IBM Isreal Local: Avi Mendelson, Intel Israel Anat Samorli, Intel Israel Publication: Gabby Silberman, IBM Toronto Workshops: Todd Austin, U of Michigan Steering Committee Rich Belgard, Consultant, Chair Jim Bondi, Texas Instruments Tom Conte, North Carolina State University Wen-mei Hwu, University of Illinois Gearold Johnson, National Tech. University Yale Patt, University of Texas at Austin Jim Smith, University of Wisconsin Mark Smotherman, Clemson University Program Committee Sarita Adve, Rice University David Bernstein, IBM Israel Jim Bondi, Texas Instruments Doug Burger, University of Texas at Austin Brad Calder, U of California at San Diego Bob Colwell, Intel Tom Conte, North Carolina State University Kemal Ebcioglu, IBM Joel Emer, Compaq Keith Farkas, Compaq Dirk Grunwald, University of Colorado Wen-Mei Hwu, University of Illinois Scott Mahlke, Hewlett Packard Scott McFarling, Microsoft Avi Mendelson, Intel Israel Soo-Mook Moon, Seoul National U, Korea Alex Nicolau, University of California at Irvine Yale Patt, University of Texas at Austin Andre Seznec, IRISA/INRIA, France John Shen, Carnegie Melon University Gabby Silberman, IBM Canada Jim Smith, University of Wisconsin Guri Sohi, University of Wisconsin Marc Tremblay, Sun Microsystems Gary Tyson, University of Michigan Mateo Valero, U Politecnica de Catalunya Uri Weiser, Intel Albert Zomaya, U of Western Australia WITH THE GENEROUS SUPPORT OF: Intel, Microsoft, HP Labs, IBM, SGI, NetVision